The present invention relates to hybrid integrated circuits, and more particularly, to high-current hybrid circuits which support power circuits on metallic substrates.
Hybrid integrated circuits (HICs) which employ ceramic substrates are widely known. However, poor heat conductance of the ceramic substrate, and high sheet resistance of the circuit patterns due to attachment with noble metal paste, make them impractical for use with high-current power circuits due to current loss and waste heat.
HICs which utilize a metallic substrate and a copper film pattern separated by an insulating resin layer are disclosed in Japanese Laid Open Publications Nos. 63-302530, 64-25554, and 64-5092. The copper film pattern has the dual role of supporting the power circuit elements and acting as a heat sink. The copper film pattern also has a plurality of terminals on the substrate soldered at prescribed positions for connection to various voltage sources and/or output lines.
The use of soldered terminals in this manner carries numerous disadvantages. First, the dedication of specific portions of the substrate to act as soldering points requires an excessive amount of space, compromising cost and spacial optimization. Second, solder oxidation deteriorates the solder layer connection to the; output current path, shortening the lifespan of the device. Third, the solder layer has a high electrical resistance, prompting current loss and producing waste heat. Thus, use of the soldered terminals in the devices of the prior art fails to adequately address the problem of supporting power circuits on metallic substrates.
A typical invertor circuit used in conjunction with prior art HICs is shown in FIG. 1. On a conventional HIC, the length of the wires connecting the electrodes of switching elements leads to high wire resistance and inductance when carrying high currents. Although external wire inductance caused by connecting an AC to DC conversion capacitor C1 can be reduced by an external snubber capacitor C2, internal inductance remains uncompensated. The resultant switching noise and voltage spikes interfere with the operation of the switching elements, producing less reliable results. For example, if switching elements SW1 and SW5 are ON, the resultant current path experiences uncompensated inductances L.sub.U1, L.sub.U2, L.sub.V2.
Similar difficulties occur in the prior-art inverter circuit shown in FIG. 8, in which each switching element consists of a plurality of high-power elements (output current loads exceeding 100 A) connected in parallel. This design unavoidably requires additional wire, causing additional inductance difficulties. These difficulties are compounded by the fact that wires of different length provide different currents to the parallel switching elements. Switching elements with short wire patterns experience higher currents than standard tolerance, that can damage the element.